Refereed International Journals (31)
Refereed Book Contributions (12)
Refereed International Conferences (92)
European Patents with International Extensions (10 Granted)
Invited Papers (Peer-reviewed) (11)
Peer-reviewed Posters with Interactive Presentation (8)
Erdős Number: 2 (Gerardo Pelosi -- Israel Koren -- Paul Erdős)
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(Author ID: 16643986100)
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(ORC ID: 0000-0002-3812-5429)
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Best Paper Award (SECRYPT 2020)
Marco Baldi, Alessandro Barenghi, Franco Chiaraluce, {\bf Gerardo Pelosi},
and Paolo Santini.
A Failure Rate Model of Bit-flipping Decoders for QC-LDPC and QC-MDPC Code-based Cryptosystems'. 17th International Joint Conference on e-Business and Telecommunications (ICETE), held remotely (due to covid-19 pandemic) on July 8 - 10, 2020.
2018 Hardware and Embedded Security ''Top Picks'' paper Award.
The paper “A Code Morphing Methodology to Automate Power Analysis Countermeasures,” appeared in Proc. of the 49th Design Automation Conference (DAC 2012), ACM, 2012, has been awarded for the most significant papers based on novelty and long-term impact from IEEE/ACM conferences and journals in the broad area of Hardware and Embedded Security during the six-year period: 2012-2017.
Presentations to the 2018 Top Picks in Hardware and Embedded Security Workshop, co-located
with IEEE/ACM ICCAD 2018 Conference, San Diego, CA, USA on November 8th, 2018, were selected from papers appeared in leading hardware and embedded security conferences and
journals including but not limited to DAC, DATE, ICCAD, HOST, CHES, ETS, VTS, ITC, IEEE
S&P, Euro S&P, Usenix Security, ASIA CCS, NDSS, ISCA, MICRO, ASPLOS, HPCA, ACSAC
and ACM CCS during the six-year period: 2012-2017.
HiPEAC Paper Award (2018)
European Network of Excellence on High Performance and Embedded Architecture and Compilation
Alessandro Barenghi and Gerardo Pelosi, Side-channel security of superscalar CPUs: Evaluating the Impact of Microarchitectural Features, in Proceedings of the 55th Design Automation Conference (DAC 2018). ACM 2018, 6 pages (ISBN: 978-1-4503-5700-5/18/06).
HiPEAC Paper Award (2015)
European Network of Excellence on High Performance and Embedded Architecture and Compilation
Gerardo Pelosi, Giovanni Agosta, Alessandro Barenghi, Michele Scandale, nformation Leakage Chaff: Feeding Red Herrings to Side Channel Attackers, in Proceedings of the 52nd Design Automation Conference (DAC 2015). ACM 2015, pp. 33:1-33:6 (ISBN: 978-1-4503-3520-1/15/06).
Best Paper Award (SIN 2014)
Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi and Michele Scandale,
Differential Fault Analysis for Block Ciphers: an Automated Conservative Analysis,
In Proceedinds of the Int.l Conf. on Security of Information and Networks (SIN '14). ACM 2014,
pp. 171:1-171:8, (ISBN: 978-1-4503-3033-6/14/09)
HiPEAC Paper Award (2014)
European Network of Excellence on High Performance and Embedded Architecture and Compilation
Gerardo Pelosi, Giovanni Agosta, Alessandro Barenghi, Michele Scandale, A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software, in Proceedings of the 51st Design Automation Conference (DAC 2014). ACM 2014, pp.210:1-210:6 (ISBN: 978-1-4503-2730-5).
HiPEAC Paper Award (2013)
European Network of Excellence on High Performance and Embedded Architecture and Compilation
Gerardo Pelosi, Giovanni Agosta, Alessandro Barenghi, Massimo Maggi, Compiler-based Side Channel Vulnerability Analysis and Optimized Countermeasures Application, in Proceedings of the 50th Design Automation Conference (DAC 2013). ACM 2013, pp. 81:1-81:6 (ISBN: 978-1-4503-2071-9).
HiPEAC Paper Award (2012)
European Network of Excellence on High Performance and Embedded Architecture and Compilation
Gerardo Pelosi, Giovanni Agosta and Alessandro Barenghi, A Code Morphing Methodology to Automate Power Analysis Countermeasures, in Proceedings of the 49th Design Automation Conference (DAC 2012).
ACM 2012 , pp. 77-82, (ISBN 978-1-4503-1199-1).
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In collaboration with the Advanced System Technology Division of STMicroelectronics, Agrate (IT) and the HP Laboratories, Bristol (UK), concerning the design of secure devices and either the definition or the optimization of cryptographic application-specific protocols.